The present invention relates to the field of semiconductor memories and is particularly related to the application of CMOS gate array circuits as read-only memories (ROMs).
A gate array or uncommitted logic array is a matrix of transistors that is defined on an integrated circuit (IC) chip up to the final stage of chip processing. The final manufacturing step usually involves patterning one or more metal layers to connect the transistors in the matrix together to realize a desired set of logic functions or gates. The gates can be interconnected to realize an desired chip function and the interconnecting wiring traces are often arranged in parallel lines between the rows of transistors.
Complementary metal oxide semiconductor (CMOS) gate arrays absorb appreciable power only when the CMOS gates switch logic states, and thus have lower average power consumption per gate than arrays employing other technologies such as bipolar. This feature is particularly important in very-large-scale-integration (VLSI) ICs which can have in excess of a million transistors on a single chip. Each CMOS gate is composed of a number of P-channel and N-channel field-effect transistors (FETS) which are interconnected appropriately; for example, typical two-input NOR and NAND gates are each composed of two P-channel and two N-channel FETs.
In employing a gate array as a memory circuit, for example a ROM, the individual transistors are directly connected in a matrix which is programmed during IC manufacturing to store bits of information in the form of the presence or absence of a transistor at each matrix intersection. Such a matrix, and the connection of the memory transistor elements between word-lines and bit-lines, is shown generally in FIG. 1. The figure shows that all of the transistors in the array are present. In actual practice, only selected ones of the memory transistors will be connected to a word line in accordance with the particular pattern of binary ones and zeroes to be stored in the memory.
Consistent with the complementary nature of CMOS, equal numbers of P-channel and N-channel transistors are formed in the matrix of a CMOS gate array. In the past, when a ROM has been realized in such a gate array, only about half of the transistors on the chip are utilized because ROMs have typically been composed of N-channel transistors only, as depicted in FIG. 1. P-channel FETs have not been used as memory elements because they have slower switching speeds than N-channel FETs of the same size. Also of particular importance in a memory device, sensing of the presence of N-channel FETs has been more reliable because they have a higher mobility (i.e. lower resistance) than P-channel devices. In addition they are complementary to the usually P-channel load FETs and level-sensing components, and thus develop an easily identified voltage difference between the logic 0 (transistor present) and logic 1 (transistor absent) states.
When P-channel transistors are used as the memory elements unavoidable IC manufacturing process variations, as well as changes in the supply voltage, can result in small, and thus difficult to detect, differences in bit-line voltage levels between the logic zero and logic one state. For example, for a typical positive power supply voltage (V.sub.cc) of 4.5 volts, the voltage difference between logic high and low states might be less than 1 volt, in contrast to the difference of at least V.sub.cc /2 (2.25 volts) and typically more for higher mobility N-channel memory transistors.
Another limitation associated with CMOS memory circuits that employ only the N-channel transistors as storage devices is their longer interconnection length. In particular, even though P-channel transistors are not used as memory elements they are still present within the IC structure. Typically, an unused P-channel transistor is located between each two N-channel memory elements. To avoid this arrangement, as well as to easily implement bit line sense amplifiers, the ROM can be custom designed and located in the periphery of the chip, with the logic gates being located in the center of the chip. This approach is not entirely desirable, because it loses the design flexibility that is afforded by gate array structures. Further, the relatively long interconnects that are required between the logic portion of the chip and the memory elements can introduce delays and routing problems.